1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for holding semiconductor chip packages during various processing steps.
2. Description of the Related Art
A typical conventional packaged semiconductor chip consists of a laminate of several layers of different materials. From bottom to top, a typical package consists of a base or carrier substrate, a die underfill material, an array of solder joints and the silicon die. For some designs, a thermal interface material and a lid or heat spreader top off the stack. Each of these layers generally has a different coefficient of thermal expansion (CTE). In some cases, the coefficients of thermal expansion for two layers, such as the underfill material and the silicon die, may differ by a factor of ten or more. Materials with differing CTE's strain at different rates during thermal cycling. The differential strain rates tend to produce warping of the package substrate and the silicon die. If the warping is severe enough, several undesirable things can occur. First, the carrier substrate can be warped to a point where some of solder joints delaminate and cause electrical failure. Second, and in the case of lid-type designs, the thermal interface material can be stretched to the point of delamination from either the semiconductor chip, the lid or both. The thermal resistance of the delaminated area can skyrocket resulting in significant heat buildup in that area which can damage the chip.
Conventional multi-chip devices can be susceptible to differential CTE substrate warping. In conventional multi-chip devices, both the substrates and bathtub or “top hat” style lids tend to be oblong. The conventional lids have a continuous internal space that is designed to accommodate two semiconductor chips mounted side-by-side on the substrate. As a result of the large internal space of the lid, the central region of the package substrate is unfettered structurally and may undergo significant thermal strains. The warping can cause delamination of the thermal interface materials of the two dice, particularly near the central region of the substrate.
Solder joint reflow is one process step where substrate warpage can be particularly dangerous. In conventional solder reflow processes, a semiconductor chip is laid on a semiconductor chip package in flip-chip orientation so that the solder bumps of the chip either contact or are in close proximity to a corresponding array of solder bumps on the package substrate and the entire arrangement is placed in a heating device such as a furnace and heated up to be reflow temperature of at least one of the arrays of solder bumps so that metallurgical bonding between the arrays of bumps establishes an array of solder joints. Whatever mismatches in CTE exist at the moment of reflow are exacerbated by the elevated temperatures.
Some manufacturers of certain types of conventional fab tools provide highly specialized types of clamping fixtures that are suitable for holding a semiconductor chip package while in a given tool. For example, Panasonic provides a fixture for holding a semiconductor chip package during a passive components placement process. Datacon provides a fixture for use in a direct placement machine while DEK provides a dedicated fixture for use in a solder printing machine. These conventional machine-specific fixtures provide only a temporary flattening of the otherwise warped package substrate. Once the substrate is removed from the particular machine, the previous warping state will tend to return quickly. If the packet substrate is then subjected to solder reflow the aforementioned solder joint damage or failure can result. Furthermore, the conventional clamping fixtures tend to use vacuum systems in order to provide the requisite clamping force and thus involve a certain level of system and operation complexity.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.